In order to provide increased flexibility in design and improve the time to market, packaging technologies (e.g., system in package (SiP), system on a chip (SoC), or the like) may include a plurality of discrete components coupled to an integrated circuit (IC) die. These additional components may be mounted to the packaging substrate, embedded within the packaging substrate, or embedded in a mold layer formed around the die. For example, components may be embedded in the mold layer formed around the die in embedded wafer level ball grid array (eWLB) or embedded panel level ball grid array (ePLB) packages. In such packages, additional components are located in the mold layer outside an outer perimeter of the die, and electrical connections from the die to the components are made with a redistribution layer (RDL) that is formed over the mold layer. Accordingly, eWLB and ePLB packages require additional surface area in the X-Y dimension in order to package the components and the die in a single mold layer.
In addition to increasing the area needed to package all of the components and the die in the same mold layer, patterning the RDL on the mold layer is limited by the minimum line width and spacing dictated by design rules. The limit for each is typically about 5 μm or greater. The line width and spacing needs to be relatively large to account for misalignment that occurs during the molding process. For example, embedded components on the edge of the wafer or panel move a significant amount due to mold flow and coefficient of thermal expansion (CTE) mismatch. The misalignment issues are becoming an even greater concern as more than one RDL is needed. Misalignment between multiple redistribution layers further decreases the reliability and yield of such packages.
Accordingly, there is a need in the art for packaging technologies that allow for the formation of reliable packages with a small footprint.